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19-0810; Rev 0; 4/07
Overvoltage Protectors with External pFET
General Description
The MAX4923-MAX4926 overvoltage protection (OVP) controllers protect low-voltage systems against high-voltage faults of up to +28V with an appropriate external pFET. When the input voltage exceeds the overvoltage lockout (OVLO) threshold, or falls below the undervoltage lockout (UVLO) threshold, these devices turn off the pFET to prevent damage to protected components and issue a flag to notify the processor of a fault condition. The typical overvoltage trip level is set to 7.18V (MAX4923), 6.16V (MAX4924), 5.65V (MAX4925), and 4.46V (MAX4926). The undervoltage trip level is set to 2.44V (typ) for all devices. The input (IN) is ESD protected to 15kV HBM when bypassed to ground with a 1F ceramic capacitor. All devices are offered in a small, 6-pin (1.5mm x 1.0mm) DFN package and are specified over the extended -40C to +85C temperature range. o Overvoltage Protection Up to +28V o Preset 7.18V, 6.16V, 5.65V, and 4.46V Typical Overvoltage Trip Levels o Preset 2.44V Typical Undervoltage Trip Level o 2.5% Accurate Overvoltage/Undervoltage Trip Levels o Low 13A (typ) Supply Current o Drives External pFET o 20ms Adapter Debounce Time o Fault Flag Indicator o 6-Pin (1.5mm x 1.0mm) DFN Package
Features
MAX4923-MAX4926
Applications
Cell Phones Digital Still Cameras PDAs and Palmtop Devices MP3 Players
INPUT +1.8V TO 28V
Typical Operating Circuit
P
OUTPUT
Pin Configuration
TOP VIEW
N.C 6 N.C 5 GATE 4
1F
1
IN
4 GATE
MAX4923-MAX4926
VIO
2
3 GND FLAG
MA4923-MAX4926
1 IN
2 GND
3 FLAG
DFN
Ordering Information/Selector Guide
PART MAX4923ELT+* MAX4924ELT+ MAX4925ELT+ PIN-PACKAGE 6 DFN 6 DFN 6 DFN OVLO (V) 7.18 6.16 5.65 UVLO (V) 2.44 2.44 2.44 TOP MARK LB LC LD PKG CODE L611-1 L611-1 L611-1
MAX4926ELT+ 6 DFN 4.46 2.44 LE L611-1 Note: All devices are specified over the -40C to +85C operating temperature range. +Denotes lead-free package. *Future Product--contact factory for availability. ________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Overvoltage Protectors with External pFET MAX4923-MAX4926
ABSOLUTE MAXIMUM RATINGS
IN, GATE to GND....................................................-0.3V to +30V FLAG to GND ...........................................................-0.3V to +6V Continuous Power Dissipation (TA = +70C) 6-DFN (derate 2.1mW/C above 70C) .......................168mW Operating Temperature Range ...........................-40C to +85C Junction Temperature .....................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300 C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = +5V for MAX4923/MAX4924/MAX4925, VIN = +4V for MAX4926, CGATE = 500pF to IN, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Input Voltage Range SYMBOL VIN MAX4923 Overvoltage Lockout Level OVLO VIN rising MAX4924 MAX4925 MAX4926 MAX4923 Overvoltage Lockout Hysteresis MAX4924 MAX4925 MAX4926 Undervoltage Lockout Level Undervoltage Lockout Hysteresis IN Supply Current GATE Voltage High GATE Pulldown Current FLAG Low Voltage FLAG Leakage Current TIMING CHARACTERISTICS Debounce Time tDEB VUVLO < VIN < VOVLO, time for GATE to go low (Figure 1) VGATE = 5V to 0.5V (MAX4923/MAX4924/MAX4925) or VGATE = 4V to 0.5V (MAX4926) (Figure 1) VIN rising at 1V/s from 5V to 8V (MAX4923/MAX4924/MAX4925) or from 4V to 7V (MAX4926) to VGATE = VIN -0.5V (Figure 1) VIN rising at 1V s from 5V to 8V (MAX4923/MAX4924/MAX4925) or from 4V to 7V (MAX4926), to VFLAG = 2.4V, RFLAG = 10k to 3V (Figure 1) 10 20 34 ms IIN VOH IPD VOL ILKG MAX4923/MAX4924/MAX4925 MAX4926 VIN > 8V, ISOURCE = 0.1mA VGATE = VIN ISINK = 1mA VFLAG = 5.5V -1 VIN 0.2 6.5 12 0.4 +1 UVLO VIN falling 2.378 CONDITIONS MIN 1.8 7.00 6.00 5.50 4.35 7.18 6.16 5.65 4.46 65 55 50 40 2.439 20 14 13 25 23 2.500 V mV A V mA V A mV TYP MAX 28.0 7.36 6.31 5.79 4.57 V UNITS V
Gate Turn-on Time
tGON
0.6
s
Gate Turn-Off Time
tGOFF
5
20
s
Flag Assertion Delay
tFLAG
4.5
s
Note 1: All devices are 100% tested at +25C. Electrical limits across the full temperature range are guaranteed by design and characterization. 2 _______________________________________________________________________________________
Overvoltage Protectors with External pFET
Typical Operating Characteristics
(VIN = +5V for MAX4923/MAX4924/MAX4925, VIN = +4V for MAX4926 (pFET = Si6991DQ), TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. INPUT VOLTAGE
MAX4923 toc01
MAX4923-MAX4926
GATE VOLTAGE vs. INPUT VOLTAGE
MAX4925 8 GATE VOLTAGE (V)
MAX4923 toc02
GATE-OUTPUT LOW VOLTAGE vs. GATE SINK CURRENT
MAX4923 toc03
100
10
250 GATE OUTPUT LOW VOLTAGE (mV)
80 SUPPLY CURRENT (A) MAX4925 60
200 VCC = +2.5V 150 VCC = +3.3V
6
40
MAX4926
4
100
20
2
50
VCC = +5.5V
0 0 4 8 12 16 20 24 28 INPUT VOLTAGE (V)
0 2 4 6 8 INPUT VOLTAGE (V)
0 0 200 400 600 800 GATE SINK CURRENT (A) 1000
SUPPLY CURRENT vs. TEMPERATURE
MAX4926 VCC = +4V 14 SUPPLY CURRENT (A)
MAX4923 toc04
POWER-UP RESPONSE
MAX4923 toc05
POWER-UP RESPONSE
MAX4923 toc06
15
VIN
5V/div 5V/div VIN 5V/div VOUT
13 5V/div 12 5V/div VFLAG 10 -40 -15 10 35 60 85 20.0 ms 10.0ms TEMPERATURE (C) VGATE 1A/div IIN 5V/div VFLAG
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OVERVOLTAGE RESPONSE
MAX4923 toc07
POWER-UP OVERVOLTAGE RESPONSE
MAX4923 toc08
5V/div
VIN 5V/div
VIN
5V/div
VGATE 5V/div
VGATE
10mA/div
IGATE
5V/div
VFLAG
5V/div VFLAG
20.0s
10.0ms
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Overvoltage Protectors with External pFET MAX4923-MAX4926
Pin Description
PIN 1 2 3 4 5, 6 NAME IN GND FLAG GATE N.C. FUNCTION Voltage Input. IN is both the power-supply input and the overvoltage/undervoltage sense input. Bypass IN to GND with a 1F ceramic capacitor as close as possible to the device to enable 15kV (HBM) ESD protection on IN. Ground Fault Indication Open-Drain Output. FLAG deasserts high during undervoltage and overvoltage lockout conditions. FLAG asserts low during normal operation. pFET Gate Drive Output. GATE is driven high during a fault condition to turn off the external pFET. When VUVLO < VIN < VOVLO, GATE is driven low and the external pFET is turned on. No Connection. Not internally connected. Leave N.C. unconnected.
Functional Diagram
IN GATE DRIVER GATE
MAX4923-MAX4926
GND
OVLO AND UVLO DETECTOR
CONTROL LOGIC AND TIMER
FLAG
VOVLO
VIN tDEB tGOFF VIN - 0.5V tDEB tGOFF
VUVLO
VIN - 0.5V
VGATE O.5V tGON tFLAG tGON
O.5V
tFLAG
3V
VFLAG
Figure 1. Timing Diagram
4 _______________________________________________________________________________________
Overvoltage Protectors with External pFET MAX4923-MAX4926
STANDBY GATE = HIGH FLAG = HIGH VUVLO < VIN < VOVLO
INPUT SYSTEM LOADS
ADAPTER WITH BUILT-IN BATTERY CHARGER
P
OUTPUT + LITHIUM ION BATTERY -
1
IN
GATE
4
VIN < VUVLO
TIME STARTS COUNTING t = 20ms
VIN > VOVLO
MAX4926
VI0
2
GND
FLAG
3
ON GATE = LOW FLAG = LOW
Figure 2. State Machine
Figure 3. MAX4926 Typical Operating Circuit
Detailed Description
The MAX4923-MAX4926 overvoltage protection controllers protect low-voltage systems against highvoltage faults of up to +28V when used with a -30V pFET. When the input voltage exceeds the OVLO threshold, these devices turn off the external pFET to prevent damage to protected components. The typical overvoltage trip level is set to 7.18V (MAX4923), 6.16V (MAX4924), 5.65V (MAX4925), and 4.46V (MAX4926). When the supply drops below the UVLO threshold, the devices turn off the external pFET. IN is ESD protected to +15kV (Human Body Model) when bypassed with a 1F ceramic capacitor to ground.
Device Operation
The MAX4923-MAX4926 have an on-board state machine to control device operation. A flowchart is shown in Figure 2. At initial power up, if VIN < VUVLO or if VIN > VOVLO, both GATE and FLAG are high. When VUVLO < VIN < VOVLO, an internal timer starts counting and the device enters its on state after a 20ms delay. At any time if VIN drops below VUVLO or above VOVLO, both GATE and FLAG transition high.
Application Information
MAX4926 Application
In a typical application for the MAX4926, an external adapter with built-in battery charger is connected to IN and a battery is connected to the drain of the external FET. When the adapter is unplugged, IN is directly connected to the battery through the external FET. Since the battery voltage is typically greater than VUVLO, the GATE voltage stays low and the device remains powered by the battery.
Undervoltage Lockout (UVLO)
The MAX4923-MAX4926 have a fixed 2.44V (typ) UVLO level. When VIN is less than VUVLO, GATE is high and FLAG is high.
Overvoltage Lockout (OVLO)
The MAX4923 has a 7.18V (typ) OVLO; the MAX4924 has a 6.16V (typ) OVLO; the MAX4925 has a 5.65V (typ) OVLO; and the MAX4926 has a 4.46V (typ) OVLO. When VIN is greater than VOVLO, GATE is high and FLAG is high.
MOSFET Selection
The MAX4923-MAX4926 are designed for use with either a single pFET or dual pFETs in parallel. MOSFETs with RDS(ON) specified for a VGS of -4.5V are recommended. For input supplies near the UVLO maximum of 2.5V, use a MOSFET specified for a lower VGS voltage. Also, the VDS must be -30V and the VGS (max) must be higher than the VOVLO (max) for the MOSFET to withstand the full +28V input range of the MAX4923-MAX4926.
FLAG Output
The open-drain FLAG output is used to signal to the host system that there is a fault with the input voltage. FLAG goes high during an overvoltage or undervoltage fault. Connect a pullup resistor from FLAG to the logic I/O voltage of the host system.
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Overvoltage Protectors with External pFET MAX4923-MAX4926
Table 1. MOSFETS Suggestions
PART Si3993DV Si1433DH Si3983DV Si1413DH Si5933DC Si6991DQ CONFIGURATON/ PACKAGE Dual/TSOP-6 Single/SOT-363 Dual/TSOP-6 Single/SOT-363 Dual/1206-8 Dual/TSSOP-8 VDS MAX (V) -30 -30 -20 -20 -20 -30 RON MAX (m) at VGS = -4.5V 245 each 260 110 each 115 110 each 68 each Vishay Siliconix www.vishay.com MANUFACTURER
RC 1M CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 1.5k DISCHARGE RESISTANCE DEVICE UNDER TEST
IP 100% 90% AMPERES
Ir
PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE)
Cs 100pF
STORAGE CAPACITOR
36.8% 10% 0 0 tRL TIME tDL CURRENT WAVEFORM
Figure 4. Human Body ESD Test Model
Figure 5. Human Body Model Current Waveform
IN Bypass Consideration
For most applications, bypass IN to GND with a 1F ceramic capacitor. If the power source has significant inductance due to long lead length, take care to prevent overshoots due to the LC tank circuit and provide protection if necessary to prevent exceeding the 30V absolute maximum rating on IN.
Human Body Model Figure 4 shows the Human Body Model and Figure 5 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest that is then discharged into the device through a 1.5k resistor.
ESD Test Conditions
The MAX4923-MAX4926 are ESD protected to 15kV (typ) Human Body Model on IN when IN is bypassed to ground with a 1F ceramic capacitor as close as possible to IN.
Chip Information
PROCESS: BiCMOS
6
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Overvoltage Protectors with External pFET
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
6L UDFN.EPS
MAX4923-MAX4926
TOPMARK 2 4 5
3
A
4
e
5
b
6 PIN 1 0.075x45
AA
PIN 1 MARK
1
E
L
A2 D TOP VIEW A1 SIDE VIEW
3
2 A A
1
L1
L2
BOTTOM VIEW
COMMON DIMENSIONS
b
A A1 A2 D E L L1 L2 b e Pkg. Code
SECTION A-A
MIN. 0.65 -0.00 1.45 0.95 0.30 0.00 0.05 0.17
NOM. 0.72 0.20 -1.50 1.00 0.35 --0.20 0.50 BSC.
MAX. 0.80 -0.05 1.55 1.05 0.40 0.08 0.10 0.23
L611-1, L611-2
TITLE:
PACKAGE OUTLINE, 6L uDFN, 1.5x1.0x0.8mm
APPROVAL DOCUMENT CONTROL NO. REV.
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21-0147
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1
2
TABLE 1
Translation Table for Calendar Year Code Calendar Year 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014
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Translation Table for Payweek Binary Coding Payweek 06-11 12-17 18-23 24-29 30-35 36-41 42-47 48-51 52-05
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TITLE:
PACKAGE OUTLINE, 6L uDFN, 1.5x1.0x0.8mm
APPROVAL DOCUMENT CONTROL NO. REV.
-DRAWING NOT TO SCALE-
21-0147
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7
(c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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